The present invention relates to a semiconductor memory, such as a mask ROM provided with a sense amplifier and an output buffer, a flash memory, or the like, and more specifically to a semiconductor memory improved in such a way as to prevent sense amplifier malfunctions due to noise generated in the output buffer.
Among semiconductor memories is a mask ROM. In the mask ROM, each memory cell is formed from a single transistor. Data can be stored by changing the threshold voltage of this transistor.
Data readout is performed by comparing a current that flows in a selected memory cell with a reference current that is set to about half of a current flowing in a memory cell storing a data "1" and amplifying the current difference in the sense amplifier. Data sensed by the sense amplifier is output through the output buffer to outside of the memory.
The operation of the output buffer is controlled by a given control signal. When the control signal is activated during an interval when the sense amplifier is operating, the output buffer may generate noise. In general, the sense amplifier is designed to be high in sensitivity. Upon receipt of the noise, therefore, the sense amplifier outputs temporarily data at opposite level, which disadvantageously lengthens access time.
FIG. 1 shows a general circuit arrangement of a sense amplifier. This sense amplifier is constructed from two pairs of P-channel MOS transistors 161, 162 and 163, 164, each pair forming a current mirror, an N-channel MOS transistor 165 having its drain-source path connected between the drain of the MOS transistor 161 and a sense node (common data line) DL supplied with a potential depending on read data from a memory cell and its gate supplied with a bias voltage BIAS, an N-channel MOS transistor 166 having its drain-source path connected between the drain of the MOS transistor 163 and a reference node (reference node) REF supplied with a reference potential produced by a reference cell RC and its gate supplied with the bias voltage BIAS, and a pair of N-channel MOS transistors 167 and 168 constituting a current mirror. The MOS transistor 167 has its drain-source path connected between the drain of the MOS transistor 164 and ground and the MOS transistor 168 has its drain-source path connected between the drain of the MOS transistor 162 and ground. Sense data SAout is taken at the common drains of the MOS transistors 162 and 168.
Here, the operation of the sense amplifier will be described briefly. When data is read from a memory cell, the sense node DL is supplied with a potential corresponding to that read data, while the reference node is supplied with the reference potential. Note that the reference potential is set to be nearly midway between the potential at the sense node DL when a data "1" is read from the memory cell and the potential at the sense node DL when a data "0" is read.
For example, when a data "0" is read out, the potential at the sense node DL becomes higher than the reference potential, so that current in the P-channel MOS transistor 164 becomes higher than that in the P-channel MOS transistor 162. As a result, sense data SAout at a low (L) level corresponding to ground potential is output. In contrast, when a data "1" is read out, the potential at the sense node DL becomes lower than the reference potential, so that current in the P-channel MOS transistor 162 becomes higher than that in the P-channel MOS transistor 164. As a result, sense data SAout at a high (H) level corresponding to supply voltage Vcc is output.
The N-channel MOS transistor 165 having its gate supplied with bias voltage BIAS is used for a voltage clamping purpose not to allow the supply voltage Vcc to be directly applied to the sense node DL. The bias voltage BIAS is set much lower than the supply voltage Vcc.
The bias voltage BIAS is generated by a bias circuit not shown. The reason why the N-channel MOS transistor 166 having its gate supplied with the bias voltage BIAS is provided on the reference node side is to match characteristics on the reference and sense node sides.
The cause of the elongation of access time in the sense amplifier is variations in bias voltage BIAS resulting from noise generated in the output buffer entering the bias circuit. When the bias voltage BIAS is increased by tens of millivolts, both the sense node DL and the reference node REF are overcharged, but their degrees of overcharging vary according to a difference between load capacitances associated with the respective nodes. For example, when a data "0" is read out, the reference node temporarily becomes higher in potential than the sense node as a result of the reference node being lower in load capacitance than the sense node being overcharged through noise, causing a data "1" (high level) to be output as sense data SAout. As a result, the access time is lengthened.
The load capacitance associated with the sense node is divided into common data line capacitance, column gate capacitance, junction capacitance of the column gate, and bit line capacitance.
Thus, if noise is generated during the sense amplifier operating period and then entered into the sense amplifier, the sense amplifier malfunctions temporarily because the sense node and the reference node in the sense amplifier differ in load capacitance. This causes the elongation of access time.
When an attempt is made to match the load capacitances associated with the sense node and the reference node in order to eliminate such a disadvantage, additional circuitry is required. This results in another disadvantage that the semiconductor chip area has to be increased.